New hardware profile: PoE AP (#141)

* New hardware profile: PoE AP

- added harware profiles for C6 firmware in menuconfig
- added free PSRAM stat in webinterface

* fix(fsfree): fixed var type of freesize of FS
This commit is contained in:
Marcel
2023-09-29 02:46:11 +02:00
committed by GitHub
parent db80d23b52
commit 5b9f8b324e
12 changed files with 140 additions and 1872 deletions

View File

@@ -2,3 +2,7 @@ build
*.axf
# Allow
!*.bin
.vscode
sdkconfig
sdkconfig.old

View File

@@ -0,0 +1,28 @@
menu "OEPL Hardware config"
choice OEPL_HARDWARE_PROFILE
prompt "Hardware profile"
default OEPL_HARDWARE_PROFILE_DEFAULT
config OEPL_HARDWARE_PROFILE_DEFAULT
bool "Default"
config OEPL_HARDWARE_PROFILE_POE_AP
bool "PoE-AP"
config OEPL_HARDWARE_PROFILE_CUSTOM
bool "Custom"
endchoice
config OEPL_HARDWARE_UART_TX
depends on OEPL_HARDWARE_PROFILE_CUSTOM
int "GPIO - UART TX"
default 3
config OEPL_HARDWARE_UART_RX
depends on OEPL_HARDWARE_PROFILE_CUSTOM
int "GPIO - UART RX"
default 2
endmenu

View File

@@ -20,6 +20,7 @@
#include "sdkconfig.h"
#include "soc/uart_struct.h"
#include "soc/lp_uart_reg.h"
#include "second_uart.h"
static const char *TAG = "SECOND_UART";
@@ -32,9 +33,6 @@ volatile int curr_buff_pos = 0;
volatile int worked_buff_pos = 0;
volatile uint8_t buff_pos[MAX_BUFF_POS + 5];
#define S3_TX_PIN 3
#define S3_RX_PIN 2
static void uart_event_task(void *pvParameters);
void init_second_uart() {
uart_config_t uart_config = {
@@ -47,7 +45,7 @@ void init_second_uart() {
};
ESP_ERROR_CHECK(uart_driver_install(1, BUF_SIZE * 2, BUF_SIZE * 2, 20, &uart0_queue, 0));
ESP_ERROR_CHECK(uart_param_config(1, &uart_config));
ESP_ERROR_CHECK(uart_set_pin(1, S3_TX_PIN, S3_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE));
ESP_ERROR_CHECK(uart_set_pin(1, CONFIG_OEPL_HARDWARE_UART_TX, CONFIG_OEPL_HARDWARE_UART_RX, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE));
xTaskCreate(uart_event_task, "uart_event_task", 16384, NULL, 12, NULL);
}

View File

@@ -1,5 +1,7 @@
#pragma once
#include <inttypes.h>
void init_second_uart();
void uart_switch_speed(int baudrate);
@@ -9,3 +11,15 @@ bool getRxCharSecond(uint8_t *newChar);
void uart_printf(const char *format, ...);
#define pr uart_printf
#if defined(CONFIG_OEPL_HARDWARE_PROFILE_DEFAULT)
#define CONFIG_OEPL_HARDWARE_UART_TX 3
#define CONFIG_OEPL_HARDWARE_UART_RX 2
#elif defined(CONFIG_OEPL_HARDWARE_PROFILE_POE_AP)
#define CONFIG_OEPL_HARDWARE_UART_TX 5
#define CONFIG_OEPL_HARDWARE_UART_RX 18
#elif defined(CONFIG_OEPL_HARDWARE_PROFILE_CUSTOM)
#if !defined(CONFIG_OEPL_HARDWARE_UART_TX) || !defined(CONFIG_OEPL_HARDWARE_UART_RX)
#error "No UART TX / RX pins defined. Please check menuconfig"
#endif
#endif

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,8 @@
# This file was generated using idf.py save-defconfig. It can be edited manually.
# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
#
CONFIG_IDF_TARGET="esp32c6"
CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE=y
CONFIG_PARTITION_TABLE_CUSTOM=y

View File

@@ -0,0 +1,8 @@
# Name, Type, SubType, Offset, Size, Flags
nvs, data, nvs, 0x9000, 0x4000
otadata, data, ota, 0xD000, 0x2000
phy_init, data, phy, 0xF000, 0x1000
app0, app, ota_0, 0x10000, 0x200000
app1, app, ota_1, 0x210000, 0x200000
spiffs, data, spiffs, 0x410000, 0xBE0000
coredump, data, coredump, 0xFF0000, 0x10000
1 # Name, Type, SubType, Offset, Size, Flags
2 nvs, data, nvs, 0x9000, 0x4000
3 otadata, data, ota, 0xD000, 0x2000
4 phy_init, data, phy, 0xF000, 0x1000
5 app0, app, ota_0, 0x10000, 0x200000
6 app1, app, ota_1, 0x210000, 0x200000
7 spiffs, data, spiffs, 0x410000, 0xBE0000
8 coredump, data, coredump, 0xFF0000, 0x10000

View File

@@ -27,7 +27,7 @@ class DynStorage {
void begin();
void end();
void listFiles();
size_t freeSpace();
uint64_t freeSpace();
private:
bool isInited;

View File

@@ -449,3 +449,53 @@ board_upload.maximum_size = 16777216
board_upload.maximum_ram_size = 327680
board_upload.flash_size = 32MB
#upload_flags = --no-stub
; ----------------------------------------------------------------------------------------
; !!! this configuration expects the PoE-AP and is work in progress right now !!!
; ----------------------------------------------------------------------------------------
[env:OpenEPaperLink_PoE_AP]
platform = https://github.com/platformio/platform-espressif32.git
board=esp32dev
board_build.partitions = 16MB_partition table.csv
build_unflags =
-D CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
-std=gnu++11
lib_deps =
${env.lib_deps}
build_flags =
-std=gnu++17
${env.build_flags}
; -D CORE_DEBUG_LEVEL=5
-D OPENEPAPERLINK_POE_AP_PCB
-D CONFIG_SPIRAM_USE_MALLOC=1
-D CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC=y
-D HAS_RGB_LED
-D BOARD_HAS_PSRAM
-mfix-esp32-psram-cache-issue
-D HAS_SDCARD
-D POWER_NO_SOFT_POWER
-D FLASHER_AP_SS=-1
-D FLASHER_AP_CLK=-1
-D FLASHER_AP_MOSI=-1
-D FLASHER_AP_MISO=-1
-D FLASHER_AP_RESET=-1
-D FLASHER_AP_POWER={-1} ;this board has no soft power control
-D FLASHER_AP_TXD=15
-D FLASHER_AP_RXD=4
-D FLASHER_AP_TEST=-1
-D FLASHER_LED=-1
-D FLASHER_RGB_LED=5
-D SD_CARD_CLK=13
-D SD_CARD_MISO=36
-D SD_CARD_MOSI=14
-D SD_CARD_SS=12
build_src_filter =
+<*>-<usbflasher.cpp>-<swd.cpp>-<espflasher.cpp>
board_build.flash_mode=qio
board_upload.maximum_size = 16777216
board_upload.maximum_ram_size = 327680
board_upload.flash_size = 16MB

View File

@@ -46,7 +46,7 @@ static void initSDCard() {
}
#endif
size_t DynStorage::freeSpace(){
uint64_t DynStorage::freeSpace(){
this->begin();
#ifdef HAS_SDCARD
return SD.totalBytes() - SD.usedBytes();

View File

@@ -67,7 +67,7 @@ void wsSendSysteminfo() {
time(&now);
static int freeSpaceLastRun = 0;
static size_t tagDBsize = 0;
static size_t freeSpace = Storage.freeSpace();
static uint64_t freeSpace = Storage.freeSpace();
sys["currtime"] = now;
sys["heap"] = ESP.getFreeHeap();
sys["recordcount"] = tagDBsize;
@@ -78,6 +78,11 @@ void wsSendSysteminfo() {
freeSpaceLastRun = millis();
}
sys["littlefsfree"] = freeSpace;
#if BOARD_HAS_PSRAM
sys["psfree"] = ESP.getFreePsram();
#endif
sys["apstate"] = apInfo.state;
sys["runstate"] = config.runStatus;
#if !defined(CONFIG_IDF_TARGET_ESP32)

View File

@@ -135,11 +135,24 @@ function connect() {
processTags(msg.tags);
}
if (msg.sys) {
let filesystem = 'filesystem free: ' + convertSize(msg.sys.littlefsfree);
if (msg.sys.littlefsfree < 31000) {
filesystem = 'filesystem <span class="blink-red" title="Generating content is paused">FULL! ' + convertSize(msg.sys.littlefsfree) + '</span>';
}
$('#sysinfo').innerHTML = 'free heap: ' + convertSize(msg.sys.heap) + ' &#x2507; db size: ' + convertSize(msg.sys.dbsize) + ' &#x2507; db record count: ' + msg.sys.recordcount + ' &#x2507; ' + filesystem;
let str = "";
str += `free heap: ${convertSize(msg.sys.heap)} &#x2507; `;
if (msg.sys.psfree) {
str += `free PSRAM: ${convertSize(msg.sys.psfree)} &#x2507; `;
}
str += `db size: ${convertSize(msg.sys.dbsize)} &#x2507; `;
str += `db record count: ${msg.sys.recordcount} &#x2507; `;
if (msg.sys.littlefsfree < 31000) {
str += `filesystem <span class="blink-red" title="Generating content is paused">FULL! ${convertSize(
msg.sys.littlefsfree
)} </span>`;
} else {
str += `filesystem free: ${convertSize(msg.sys.littlefsfree)}`;
}
$("#sysinfo").innerHTML = str;
if (msg.sys.apstate) {
$("#apstatecolor").style.color = apstate[msg.sys.apstate].color;
$("#apstate").innerHTML = apstate[msg.sys.apstate].state;