Specs
- TI CC1311R3 - 48Mhz Arm® Cortex®-M4 352kB Flash / 32kB RAM
- 6.4 x 3.5 in ePaper display (BWR or BWY) 800x480px
- 6x CR2450 button cell
- MX25V8006E 1 Mbyte SPI flash.
- SubGhz (868 Mhz / 915 Mhz) Radio
- FCC ID: VC-A001681
Status
An OEPL port is underway and progressing nicely ...
This port is currently able to download screen updates from the AP and display them on Chroma Aeon 74 displays.
Caution
This code is NOT ready for prime time nor is it advisable to run the tag from batteries yet.
Currently the "sleep" current consumption is currently 4 ma, i.e. broken.
Since these displays are currently rare and only a few have made their way
into the hands of hobbyists it's a low priority project.
See https://github.com/skiphansen/Tag_FW_CC13xx for source code and more information.
Programming
An xds110 or other cJTAG programmer is needed to program the CC1311.
| Supported | SN Format | Board Rev | Controller | EPD Panel | Notes |
|---|---|---|---|---|---|
| N | SRxxxxxxxxC | edk710 Issue 1 220-0001552-01 2023 |
UC8179C | FPC-7911 | BWY Version. Image with traced tracks |
CC1311R3 Pin connections
| Pin | Pin name | Usage | Notes |
|---|---|---|---|
| 1 | RF_P | antenna matching network | note 1 |
| 2 | RF_N | antenna matching network | note 1 |
| 3 | RF_TX | External LNA bias | note 1 |
| 4 | X32K_Q1 | 32786 Crystal | |
| 5 | X32K_Q2 | 32786 Crystal | |
| 6 | DIO_1 | EPD_CS | EPD pin 12 |
| 7 | DIO_2 | n/c ? | |
| 8 | DIO_3 | n/c ? | |
| 9 | DIO_4 | EPD_PWR | |
| 10 | DIO_5 | EPD_SDI | EPD pin 14 |
| 11 | DIO_6 | EPD_SCLK | EPD pin 13 |
| 12 | DIO_7 | n/c ? | |
| 13 | VDDS2 | VDD | |
| 14 | DIO_8 | UART RX (Serial in Chroma <- PC) | TP19 |
| 15 | DIO_9 | UART TX (Serial out Chroma -> PC) | TP17 |
| 16 | VDDS3 | VDD | |
| 17 | DCOUPL | Cap | |
| 18 | JTAG_TMSC | cJTAG Data | TP13 |
| 19 | JTAG_TCKC | cJTAG Clock | TP15 |
| 20 | DIO_10 | EPD_RST | EPD pin 10 |
| 21 | DIO_11 | EPD_BUSY | EPD pin 9 |
| 22 | DIO_12 | ||
| 23 | DIO_13 | ||
| 24 | DIO_14 | ||
| 25 | DCDC_SW | ||
| 26 | VDDS_DCDC | VDD | |
| 27 | RESET_N | Reset | TP12 |
| 28 | DIO_15 | ||
| 29 | DIO_16 | ||
| 30 | DIO_17 | ||
| 31 | DIO_18 | SPI_FLASH_MISO | SPI flash pin 5 |
| 32 | DIO_19 | SPI_FLASH_CS | SPI flash pin 1 |
| 33 | DIO_20 | SPI_FLASH_CLK | SPI flash pin 6 |
| 34 | DIO_21 | SPI_FLASH_MOSI | SPI flash pin 2 |
| 35 | DIO_22 | ||
| 36 | VDDS | ||
| 37 | VDDR | ||
| 38 | X48M_N | 48 Mhz crystal | |
| 39 | X48M_P | 48 Mhz crystal | |
| 40 | VDDR_RF |
Notes:
- i.e. "External Bias, Differential mode.
Tag Serial Number location
The tag's serial number is stored in the CC1311's internal flash at offset 0x2000 ! Which will complicate the installation of OEPL firmware!
SR01234567C:
00002000 53 52 01 12 35 67 43 00 ff ff ff ff ff 20 03 e0 |SR..1sC...... ..|
SPI Flash Memory Map
EEPROM size: 0x10.0000 / 1024k / 1 Megabyte.
Image size: (800 x 640 x 2 bits/pixel) / 8 bits / byte = 128,000 bytes, rounded up to erase boundary = 131,072 / 0x2.0000.
| Start Adr | End Adr | Size | Usage | Notes |
|---|---|---|---|---|
| 0x0.0000 | 0x0.0fff | 4k | OEPL Settings | |
| 0x0.1000 | 0x1.ffff | 124k | not used | |
| 0x2.0000 | 0x2.ffff | 128k | Image slot 0 | 1 |
| 0x4.0000 | 0x4.ffff | 128k | Image slot 1 | 1 |
| 0x6.0000 | 0x6.ffff | 128k | Image slot 2 | 1 |
| 0x8.0000 | 0x9.ffff | 128k | Image slot 3 | 1 |
| 0xa.0000 | 0xb.ffff | 128k | Image slot 4 & OTA image start |
2 |
| 0xc.0000 | 0xd.ffff | 128k | Image slot 5 & OTA image |
3 |
| 0xe.0000 | 0xf.ffff | 128k | Image slot 6 & OTA image |
3 |
Notes:
- Will not be clobbered by FW update so can be used for a static image.
- Will be clobbered by FW update. The OELP protocol will download non-static image again after a successful OTA when necessary.
- Might be clobbered by FW update depending on FW size. The OELP protocol will download image again after a successful OTA when necessary.
EPD controller
The display is compatible with the Waveshare 7.5inch e-Paper B V2 panel.
The EPD controller is compatible with the Ultra Chip UC8179C with LUTs programmed into the controllers OTP memory.
This means that the same FW image and be used for both BWR and BWY displays unlike the older Chroma tags that didn't use OTP for LUT storage.
Battery Current
The stock factory firmware averages about 580 nanoamps while sleeping, 1.36 microamps waking up to check for data and 6 milliamps while updating the screen.